This invention relates to an improvement in the memory elements of a read only memory and the manufacturing method of the same.
Read only memory in which information is written in during the wafer manufacturing stage is generally known as mask programmable ROM. Some of the prior art methods of writting data into a mask programmable ROM are (1) the contact method, (2) the field oxide film method, (3) the threshold voltage method. In the contact method, logical 1 or logical 0 is written in depending on whether or not the output signal line (bit line) and the drain of the memory cell transistor are connected. In the field oxide film method, data is written in by whether a gate oxide film or a field oxide film is formed on the gate region of the memory cell transistor. Namely, when a gate oxide film is formed, the memory cell transistor is turned ON and OFF by the gate voltage and, when a field oxide film is formed, the transistor is always OFF. Data is written in by these changes in the state of the memory cell transistors. In the threshold voltage method, data is written in by varying the threshold voltage Vth of the memory cells by varying the density of the impurities in the gate region of the memory cell transistor.
FIG. 1 shows an expanded plan view of part of a memory using the threshold voltage method. FIG. 1 shows the positional relationship of the individual parts, and parts not required are omitted to facilitate the illustration. In this case, the memory cells are N channel type MOS transistors, and the description is of one of the memory cells of a pair of memory cells that share a common drain. The memory cell 1, shown by a one-dot broken line, is formed of a gate 3, drain 5, source 7, polycrystalline silicon gate electrode 9 and aluminum wire layer 11 (bit line) that crosses the gate electrode 9 at right angles. The Al wire layer 11 is connected to the drain 5 by contact 13. Memory cell 1 is isolated from the contiguous memory cells by the P type isolation region 15. Source 27 is connected in common to the sources of the contiguous memory cells by N.sup.+ type regions 17, and is kept at ground level, for example.
The above prior art methods, however, have the following drawbacks. In the contact method, one contact is required for each memory cell so the memory cell is larger than those of the other methods. In the field oxide film method, data is written into the memory cell in the initial stage of wafer manufacturing so the turnaround time is long. In the threshold voltage method, on the other hand, the turnaround time is comparatively short and the memory cells are comparatively small so this method has come to be widely used. As was disclosed in "Late implant turns ROMs around fast" in ELECTRONICS, May 1983, p 50, ion implantation of the gate region of the memory cell after the formation of the Al wire has been developed. With this method it is possible to form a mask programmable ROM with very short turnaround time. Also, before data is written into the ROM, it is possible to check the characteristics of the memory cell transistors so it is possible to estimate the yield. With this method, because ion implantation is performed after the Al wire is formed, it is not possible to place it over the gate region of the memory cell and, accordingly, the planar structure of the memory cell is as shown in FIG. 2. FIG. 3 shows a cross section along the arrowed line I--I of the memory cell shown in FIG. 2. In both FIGS. 2 and 3, unrelated parts have been omitted to facilitate illustration of the positional relationship. For the purpose of illustration the memory cells are taken to be N channel MOS transistors of which one is described. The one-dot broken line shows memory cell 21, which is constructed of gate 25 formed in the P type semiconductor substrate 23, drain 27, source 29, insulation film 31, polycrystalline silicon gate electrode 33 (word line) formed over the gate 25 with insulation film 31 therebetween, and Al wire layer 37 (bit line), which is formed across gate electrode 33 at right angles and insulated therefrom by an insulation layer 35. Al wire layer 37 protrudes above drain 27 and this protrusion is connected to drain 27 by contact 39. This memory cell 21 is isolated from other elements by a P type isolation region 41. The source 29 is connected to the sources of memory cells contiguous to it by N type regions 43, and maintained at ground level, for example. For convenience of explanation, description of the passivation layer has been omitted.
However, with the construction shown in FIGS. 2 and 3, the Al wire layer 37 contacts drain 27 and must be provided so as to avoid overlapping gate 25. A gap must be maintained such that Al wire 37 does not short other Al wires and the width of the Al wire 37 must be sufficient to prevent severing of the wires during manufacturing. Also, contact 39 cannot be made too small because of manufacturing restrictions and because the contact resistance must be kept to a certain limit. Further, the portion protruding over drain 27 of Al wire 37 must have sufficient size to cover contact 39. Accordingly, the size of the memory cell 2l in the direction of the gate electrode 33 is determined by the width of Al wire 37 and the size of the gap, and the size of contact 39. This means that the transistor of this kind of memory cell is comparatively large and, consequently, it has been impossible to increase the degree of integration of the memory cells (having a structure such as that shown in FIG. 2) using the prior art threshold voltage method. The yield also is low, the cost prohibitive and the delay in the word line direction long.